FIGS. 1 and 2 taken together illustrate in block diagram format the current structure of a car's audio receiver found in a Sirius™ Satellite Digital Audio Radio Service (SDARS) system (operating in the radio frequency (RF) spectrum 2.3-GHz “Short wave” S band, from 2320 to 2345 MHz). The SDARS system has two separate front end RF signal receiving paths, one acting as a time division multiplexing (TDM) receiver (shown in FIG. 1) and the other acting as a coded orthogonal frequency division multiplexing (COFDM) receiver (shown in FIG. 2). Thus the current system requires two separate automatic gain control (AGC) controllers, a TDM AGC and a COFDM AGC, to maintain for independent demodulation the received RF signal's corresponding signal levels (respectively referred to hereinafter as “SetPoint_TDM_dB_LSB” and “SetPoint_OFDM_dB_LSB”).
Referring now specifically to FIG. 1, the TDM integrated receiver 1 of the SDARS is constructed of well-known electronic circuitry devices. RF signals (consisting of multiple digital signals or analog signals carrying digital data) are received by the TDM antenna 2 and routed to an antenna RF processing circuit 3 and an RF/IF processing circuit 4 where decoding of the radio signals begins. Input control of the automatic gain control of both the RF signals and intermediate frequency (IF) signals is handled by the TDM AGC controller 5. TDM AGC covers a dynamic power range for the TDM received RF signal of up to 75 dB. The TDM receiver signal path has a signal set-point value level defined as SetPoint_TDM_dB_LSB=(9.2+1.2) dB and this allows enough headroom to avoid any saturation happening at a 10-bit analog to digital converter (ADC) 6, which converts the RF signals to discrete digital numbers, even during TDM on-channel blocking.
After analog to digital conversion, the TDM received RF signal is routed to a digital down converter (DDC) 7 where it is split into two separate signals labeled as TDM1 and TDM2 as shown. The two signals are then separately demodulated by TDM1 demodulator 8 and TDM2 demodulator 9, respectively. The TDM received RF demodulated signal, indicated on FIG. 1 by reference labels TDM1 post-power and TDM2 post-power, are routed to the maximal function 10, which selects the maximal post power of TDM1 and TDM2 for output.
Hence, as can be seen for the TDM AGC, computation of the AGC gains required for the respective RF and IF processing circuits 3 and 4 are based solely upon the post-power level of TDM received RF signal after the maximal function 10.
With regard to control of the RF AGC gain in the TDM integrated receiver 1 of the SDARS, three rfstates (−1, 0, 1) are implemented with the initial state of the rfstates being set to 0. Any change of the rfstates depends on the information of the RF detector/direction sent from RF processing circuit 3. Additionally the step-size is 10 dB, and this means the RF AGC gain may be −10 dB, 0 dB or +10 dB. The IF AGC gain, on the other hand, ranges from −27.5 dB to +27.5 dB in 1 dB step-size. A Least Mean Square (LMS) algorithm is implemented to update the IF AGC gain. Both the RF AGC gain and the IF AGC gain are updated at 100 Hz normally, however, the updating frequency of the RF/IF AGC gains is reduced to 50 Hz to avoid problems associated with overshooting when the RF AGC gain changes.
Referring now specifically to FIG. 2, the COFDM integrated receiver 11 of the SDARS is likewise constructed of well-known electronic circuitry devices. After receipt of the COFDM RF signal (consisting of broadcast digital audio and/or video signals (DAB and DVB-T)) from the COFDM antenna 12, the antenna RF processing circuit 13, RF/IF processing circuit 14, 10-bit ADC 16, DDC 17 and COFDM demodulator 18 all operate similarly to their cousins in the TDM integrated receiver, albeit with the COFDM demodulator 18 utilizing Fast Fourier Transform implementations for integration purposes. COFDM AGC, however, covers a dynamic power range for the COFDM received RF signal of up to 131 dB, and the set-point values in COFDM pre-power and post-power are (32.2+3.0+10=45.2 dB) and (32.2+3.0=35.2 dB), respectively. The pre-power, which includes the power of un-used tones, interference noise and others, is set to 10 dB higher than the post-power.
Hence, as can be seen for the COFDM AGC, computation for the COFDM AGC controller 15 to adjust the gain levels in RF and IF processing circuits 13 and 14 require both pre-power input from the DDC 17 and post-power input from COFDM demodulator 18.
With regard to control of the RF AGC gain in the COFDM integrated receiver 11 of the SDARS, five rfstates (1, 2, 3, 4, 5) are implemented with the initial state of the rfstates being set to 3. Any change of rfstates depends on the information of RF detector/direction from RF processing circuit 13. Additionally the step-size is 15 dB, and this means the RF AGC gain may be −30 dB, −15 dB, 0 dB, +15 dB or +30 dB. The IF AGC gain, on the other hand, ranges from −35.5 dB to +35.5 dB with a 1 dB step-size. An LMS algorithm is implemented to update the IF AGC gain. Both RF AGC gain and IF AGC gain are updated at 100 Hz normally, however, the updating frequency for the RF/IF AGC gains is reduced to 50 Hz to avoid overshooting problem while the RF AGC gain changes.
As can be seen then, two independent ADC controllers are needed by the SDARS system to complete the signal processing and maintain adequate performance over a range of input signal levels. Power consumption by the system, relatively speaking, is high, and operational specifications indicate there is room for increased performance. The next generation SDARS systems will need to provide better performance with lower power consumption characteristics at reduced costs.